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a29l400 series 512k x 8 bit / 256k x 16 bit cmos 3.0 volt - only, preliminary boot sector flash memory preliminary (october, 2002, ve rsion 0.2) 1 amic technology, inc. features n single power supply operation - full voltage range: 2.7 to 3.6 volt read and write operations for battery - powered applications - regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors n access times: - 70/90 (max.) n current: - 4 ma typical active read current - 20 ma typical program/erase current - 200 na typical cmos standby - 200 n a automatic sleep mode current n flexible sector architecture - 16 kbyte/ 8 kbytex2/ 32 kbyte/ 64 kbytex7 sectors - 8 kword/ 4 kwordx2/ 16 kword/ 32 kwordx7 sectors - any combination of sectors can be erased - supports full chip erase - sector protection: a hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. temporary sector unprotect feature allows code changes in previously locked sectors n extended operating temperature range: - 45 c ~ +85 c for ? u ser ies n unlock bypass program command - reduces overall programming time when issuing multiple program command sequence n top or bottom boot block configurations available n embedded algorithms - embedded erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - embedded program algorithm automatically writes and verifies data at specified addresses n typical 100,000 program/erase cycles per sector n 20 - year data retention at 125 c - reli able operation for the life of the system n compatible with jedec - standards - pinout and software compatible with single - power - supply flash memory standard - superior inadvertent write protection n data polling and toggle bits - provides a so ftware method of detecting completion of program or erase operations n ready / busy pin (ry / by ) - provides a hardware method of detecting completion of program or erase operations (not available on 44 - pin sop) n erase suspend/erase resume - suspends a sector erase operation to read data from, or program data to, a non - erasing sector, then resumes the erase operation n hardware reset pin ( reset ) - hardware method to reset the device to reading array data n pac kage options - 44 - pin sop or 48 - pin tsop (i) or 48 - ball tfbga
a29l400 series preliminary (october, 2002, version 0.2) 2 amic technology, inc. general description the a29l400 is an 4mbit, 3.0 volt - only flash memory organized as 524,288 bytes of 8 bits or 262,144 words of 16 bits each. the 8 bits of data appear on i/o 0 - i/o 7 ; the 16 bi ts of data appear on i/o 0 ~i/o 15 . the a29l400 is offered in 48 - ball tfbga, 44 - pin sop and 48 - pin tsop packages. this device is designed to be programmed in - system with the standard system 3.0 volt vcc supply. additional 12.0 volt vpp is not required for in - system write or erase operations. however, the a29l400 can also be programmed in standard eprom programmers. the a29l400 has the first toggle bit, i/o 6 , which indicates whether an embedded program or erase is in progress, or it is in the erase suspend. be sides the i/o 6 toggle bit, the a29l400 has a second toggle bit, i/o 2 , to indicate whether the addressed sector is being selected for erase. the a29l400 also offers the ability to program in the erase suspend mode. the standard a29l400 offers access times o f 70 and 90ns, allowing high - speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the a29l400 is entirely software command set compatible wi th the jedec single - power - supply flash standard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state - machine that controls the erase and programming circuitry. writ e cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by writing the proper program command sequ ence. this initiates the embedded program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. device erasure occurs by executing the proper erase command sequence. this initiates the embe dded erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper erase marg in. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. the host system can detect whether a program or erase operation is complete by observing the ry / by pi n, or by reading the i/o 7 ( data polling) and i/o 6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sec tors to be erased and reprogrammed without affecting the data contents of other sectors. the a29l400 is fully erased when shipped from the factory. the hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. this can be achieved via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for er asure. true background erase can thus be achieved. the hardware reset pin terminates any operation in progress and resets the internal state machine to reading array data. the reset pin may be tied to the system reset c ircuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot - up firmware from the flash memory. the device offers two power - saving features. when addresses have been stable for a specified amount of time, t he device enters the automatic sleep mode. the system can also place the device into the standby mode. power consumption is greatly reduced in both these modes.
a29l400 series preliminary (october, 2002, version 0. 2) 3 amic technology, inc. pin configurations n sop n tsop (i) nc a17 a7 a6 a5 a4 a3 a2 a1 a0 ce vss oe i/o 0 i/o 14 i/o 8 i/o 7 i/o 15 (a-1) vss byte a16 a15 a14 a12 a11 a10 we a8 a9 a13 a29l400 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ry/by reset 17 18 19 20 21 22 28 27 26 25 24 23 i/o 1 i/o 9 i/o 2 i/o 10 i/o 3 i/o 11 i/o 6 i/o 13 i/o 5 i/o 12 i/o 4 vcc a29l400v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a14 a13 a12 a11 a10 a9 a8 nc we reset nc nc ry/by nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 i/o 2 i/o 10 i/o 3 i/o 11 vcc i/o 4 i/o 12 i/o 5 i/o 13 i/o 6 i/o 14 i/o 7 i/o 15 (a-1) vss byte a16 a15 nc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 i/o 9 i/o 1 i/o 8 i/o 0 oe vss ce a0 a17 a7 a6 a5 a4 a3 a2 a1 n tf bga a6 b6 c6 d6 e6 f6 g6 h6 tfbga top view, balls facing down a5 b5 c5 d5 e5 f5 g5 h5 a4 b4 c4 d4 e4 f4 g4 h4 a3 b3 c3 d3 e3 f3 g3 h3 a2 b2 c2 d2 e2 f2 g2 h2 a1 b1 c1 d1 e1 f1 g1 h1 a13 a12 a14 a15 a16 byte i/o 15 (a-1) vss a9 a8 a10 a11 i/o 7 i/o 14 i/o 13 i/o 6 we reset nc nc i/o 5 i/o 12 vcc i/o 4 ry/by nc nc nc i/o 2 i/o 10 i/o 11 i/o 3 a7 a17 a6 a5 i/o 0 i/o 8 i/o 9 i/o 1 a3 a4 a2 a1 a0 ce oe vss
a29l400 series preliminary (october, 2002, version 0. 2) 4 amic technology, inc. block diagram pin descriptions pin no. description a0 - a17 address inputs i/o 0 - i/o 14 data inputs/outputs i/o 15 data input/output, word mode i/o 15 (a - 1) a - 1 lsb address input, byte mode ce chip enable we write enable oe output enable reset hardware reset byte selects byte mode or word mode ry/ by ready/ busy - output vss ground vcc power supply nc pin not connected internally state control command register address latch x-decoder y-decoder chip enable output enable logic cell matrix y-gating vcc detector pgm voltage generator data latch input/output buffers erase voltage generator vcc vss we ce oe a 0 -a 17 i/o 0 - i/o 15 (a-1) timer stb stb reset sector switches byte ry/by
a29l400 series preliminary (october, 2002, version 0. 2) 5 amic technology, inc. absolute maximum ratings* storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 c to + 70 c . . . . . . . . . . . . . . . . . . . . . . for - u series: - 45 c to +85 c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to + 70 c . . . . . . . . . . . . . . . . . . . . . . for - u series: - 45 c to + 85 c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to +4.0v a9, oe & reset (note 2) . . . . . . . . . . . . - 0.5 to +12.5v all other pins (note 1) . . . . . . . . . . . . - 0.5v to vcc + 0.5v output short circuit current (note 3) . . . . . . . . . 200ma notes: 1. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, input or i/o pins may undershoot vss to - 2.0v for periods of up to 20ns. maximu m dc voltage on input and i/o pins is vcc +0.5v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0v for periods up to 20ns. 2. minimum dc input voltage on a9, oe and reset is - 0.5v. during voltage transitions, a9, oe and reset may overshoot vss to - 2.0v for periods of up to 20ns. maximum dc input voltage on a9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. 3. no more than one output is shorted at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. operating ranges c ommercial (c) devices ambient temperature (t a ) . . . . . . . . . . . . . . 0 c to +70 c extended range devices ambient temperature (t a ) . . . . . . . . . . . . - 45 c to +85 c vcc supply voltages vcc for all devices . . . . . . . . . . . . . . . . . . +2 .7v to +3.6v operating ranges define those limits between which the functionally of the device is guaranteed. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal co mmand register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the registe r serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections des cribe each of these operations in further detail. table 1. a29l400 device bus operations i/o 8 - i/o 15 operation ce oe we reset a0 ? a17 (note 1) i/o 0 - i/o 7 byte =v ih byte =v il read l l h h a in d out d out i/o 8 ~i/o 4 =high - z i/o 15 =a - 1 write l h l h a in d in d in high - z cmos standby vcc 0.3 v x x vcc 0.3 v x high - z high - z high - z output disable l h h h x high - z high - z high - z hardware reset x x x l x high - z high - z high - z sector protect (see note 2) l h l v id sector address, a6=l, a1=h, a0=l d in x x sector unprotect (see note 2) l h l v id sector address, a6=h, a1=h, a0=l d in x x temporary sector unprotect x x x v id a in d in d in x legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5v, x = don't care, d in = data in, d out = data out, a in = address in notes: 1. addresses are a17:a0 in word mode ( byte = v ih ), a17: a - 1 in byte mode ( byte = v il ). 2. see the ?sector protection/unprotection? section and temporary sector unprotect for more information.
a29l400 series preliminary (october, 2002, version 0. 2) 6 amic technology, inc. word/byte configuration the byte pin determines whether the i/o pins i/o 15 - i/o 0 operate in the byte or word co nfiguration. if the byte pin is set at logic ?1?, the device is in word configuration, i/o 15 - i/o 0 are active and controlled by ce and oe . if the byte pin is set at logic ?0?, t he device is in byte configuration, and only i/o 0 - i/o 7 are active and controlled by ce and oe . i/o 8 - i/o 14 are tri - stated, and i/o 15 pin is used as an input for the lsb(a - 1) address function. requirements for readin g array data to read array data from the outputs, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. oe is the output control a nd gates array data to the output pins. we should remain at v ih all the time during read operation. the byte pin determines whether the device outputs array data in words and bytes. the internal state machine is set for reading array data upon device power - up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor re ad cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see "reading array data" for more information. re fer to the ac read operations table for timing specifications and to the read operations timings diagram for the timing waveforms, l cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/co mmand sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce to v il , and oe to v ih . for program operations, the byte pin determines whether the device accepts program data in bytes or words, refer to ?word/byte configuration? for more information. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ? word / byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequence. an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address range that each sector occupies. a "sector address" consists of the address inputs required to uniquely select a sector. see the "command definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on i/o 7 - i/o 0 . standard read cycle timings apply in this mode. refer to the "autoselect mode" and "autoselect command sequence" sections for more in formation. i cc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification tables and timing diagrams for write operations. program and erase operation sta tus during an erase or program operation, the system may check the status of the operation by reading the status bits on i/o 7 - i/o 0 . standard read cycle timings and i cc read specifications apply. refer to "write operation status" for more information, an d to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe input. the device enters the cmos standby mode when the ce & reset pins are both held at v cc 0.3v. (note that this is a more restricted voltage range than v ih .) if ce and reset are held at v ih , but not within v cc 0.3v, the device will be in the standby mode, but the standby current will be greater. the device requires the standard access time (t ce ) before i t is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 and i cc4 in the dc characteristics tables represent the standby current specification. automatic s leep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc +30ns. the automatic sleep mode is independent of the ce , we and oe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents th e automatic sleep mode current specification.
a29l400 series preliminary (october, 2002, version 0. 2) 7 amic technology, inc. output disable mode when the oe input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. reset : hardware reset pin th e reset pin provides a hardware method of resetting the device to reading array data. when the system drives the reset pin low for at least a period of t rp , the device immediately terminates any operation in progress, t ristates all data output pins, and ignores all read/write attempts for the duration of the reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset pulse. when reset is held at vss 0.3v, the device draws cmos standby current (i cc4 ). if reset is held at v il but not within vss 0.3v, the standby current will be greater. the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system t o read the boot - up firmware from the flash memory. if reset is asserted during a program or erase operation, the ry/ by pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time t re ady (during embedded algorithms). the system can thus monitor ry/ by to determine whether the reset operation is complete. if reset is asserted when a program or erase operation is not executing (ry/ by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset pin return to v ih . refer to the ac characteristics tables for reset parameters and diagram.
a29l400 series preliminary (october, 2002, version 0. 2) 8 amic technology, inc. table 2. a29l400 top boot block sector address table address range (in hexadecimal) sector a17 a16 a15 a14 a13 a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 0 0 0 x x x 64/32 00000h - 0 ffffh 00000h - 07fffh sa1 0 0 1 x x x 64/32 10000h - 1ffffh 08000h - 0ffffh sa2 0 1 0 x x x 64/32 20000h - 2ffffh 10000h - 17fffh sa3 0 1 1 x x x 64/32 30000h - 3ffffh 18000h - 1ffffh sa4 1 0 0 x x x 64/32 40000h - 4ffffh 20000h - 27fffh sa5 1 0 1 x x x 64/32 50000h - 5ffffh 28000h - 2ffffh sa6 1 1 0 x x x 64/32 60000h - 6ffffh 30000h - 37fffh sa7 1 1 1 0 x x 32/16 70000h - 77fffh 38000h - 3bfffh sa8 1 1 1 1 0 0 8/4 78000h - 79fffh 3c000h - 3cfffh sa9 1 1 1 1 0 1 8/4 7a000h - 7bfffh 3d000h - 3dfffh sa10 1 1 1 1 1 x 16/8 7c000h - 7ffffh 3e000h - 3ffffh table 3. a29l400 bottom boot block sector address table address range sector a17 a16 a15 a14 a13 a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 0 0 0 0 0 x 16/8 00000h - 03fffh 00000h - 01fffh sa1 0 0 0 0 1 0 8/4 04000h - 05fffh 02000h - 02fffh sa2 0 0 0 0 1 1 8/4 06000h - 07fffh 03000h - 03fffh sa3 0 0 0 1 x x 32/16 08000h - 0ffffh 04000h - 07fffh sa4 0 0 1 x x x 64/32 10000h - 1ffffh 08000h - 0ffffh sa5 0 1 0 x x x 64/32 20000h - 2ffffh 10000h - 17fffh sa6 0 1 1 x x x 64/32 30000h - 3ffffh 18000h - 1ffffh sa7 1 0 0 x x x 64/32 40000h - 4ffffh 20000h - 27fffh sa8 1 0 1 x x x 64/32 50000h - 5ffffh 28000h - 2ffffh sa9 1 1 0 x x x 64/32 60000h - 6ffffh 3000 0h - 37fffh sa10 1 1 1 x x x 64/32 70000h - 7ffffh 38000h - 3ffffh autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on i/o 7 - i/o 0 . this mode is p rimarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in - system through the command register. when using programming eq uipment, the autoselect mode requires v id (11.5v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear o n the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on i/o 7 - i/o 0 .to access the autoselect codes in - system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see "command definitions" for details on using the autoselect mode.
a29l400 series preliminary (october, 2002, version 0. 2) 9 amic technology, inc. table 4. a29l400 autoselect codes (high voltage method) description mode ce oe we a17 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 i/o 8 to i/o 15 i/o 7 to i/o 0 manufacturer id: amic l l h x x v id x l x l l x 37h word b3h 34h device id: a29l400 (top boot block) byte l l h x x v id x l x l h x 34h word b3h b5h device id: a29l400 (bottom boot block) byte l l h x x v id x l x l h x b5h continuation id l l h x x v id x l x h h x 7fh x 01h (protected) sector protection verification l l h sa x v id x l x h l x 00h (unprotected) l=logic low= v il , h=logic high=v ih , sa=sector address , x=don?t care. note: the autoselect codes may also be accessed in - system via command sequences.
a29l400 series preliminary (october, 2002, version 0.2) 10 amic technology, inc. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotecti on feature re - enables both program and erase operations in previously protected sectors. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection / unprotection can be implemented via two methods. the primary method requires vid on the reset pin only, and can be implemented either in - system or via programming equipment. figure 2 shows the algorithm and the sector protect / unprotect timing diagram illustrates the timing waveforms for this feature. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method must be implemented using pr ogramming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see "autoselect mode" fo r details. hardware data protection the requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power - up transitions, or from system noise. the device is powered up to read array data to avoid accidentally writing data to t he array. write pulse "glitch" protection noise pulses of less than 5ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe =v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power - up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically res et to reading array data on the initial power - up. temporary sector unprotect this feature allows temporary unprotection of previous protected sectors to change data in - system. the sector unprotect mode is activated by setting the reset p in to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset pin, all the previously protected sectors are protected again. figure 1 shows the al gorithm, and the temporary sector unprotect diagram shows the timing waveforms, for this feature. start reset = v id (note 1) perform erase or program operations reset = v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation
a29l400 series preliminary (october, 2002, version 0.2) 11 amic technology, inc. start plscnt=1 reset=v id wait 1 us first write cycle=60h? set up sector address sector protect write 60h to sector address with a6=0, a1=1, a0=0 wait 150 us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h? protect another sector? remove v id from reset write reset command sector protect complete sector protect algorithm temporary sector unprotect mode increment plscnt plscnt =25? device failed no no no yes reset plscnt=1 yes yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address start plscnt=1 reset=v id wait 1 us first write cycle=60h? no temporary sector unprotect mode yes no all sectors protected? set up first sector address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect : write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h? last sector verified? remove v id from reset write reset command sector unprotect complete yes yes set up next sector address no yes yes sector unprotect algorithm increment plscnt plscnt= 1000? device failed yes no no figure 2. in-system sector protect/unprotect algorithms
a29l400 series preliminary (october, 2002, version 0.2) 12 amic technology, inc. command definitions writing specific address and data commands or sequences into the command register initiates device operat ions. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the appropriate timing diagrams in the "ac characte ristics" section. reading array data the device is automatically set to reading array data after device power - up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded eras e algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase - suspended sectors, the device outpu ts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see "erase suspend/erase resume commands" for more information on this mode. the system must issue the r eset command to re - enable the device for reading array data if i/o 5 goes high, or while in the autoselect mode. see the "reset command" section, next. see also "requirements for reading array data" in the "device bus operations" section for more informati on. the read operations table provides the read parameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this c ommand. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is co mplete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, howeve r, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if i/o 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the auto select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that sh own in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device th en enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code and another read cycle at xx03h retrieves the continuatio n code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector ad dresses. the system must write the reset command to exit the autoselect mode and return to reading array data. word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte pi n. programming is a four - bus - cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set - up command. the program address and data are written next, which in turn initiate the embedded program a lgorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the programmed cell margin. table 5 shows the address and data requirements for the byte program c ommand sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are longer latched. the system can determine the status of the program operation by using i/o 7 , i/o 6 , or ry/ by . see ?write operation status? for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte program comman d sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may h alt the operation and set i/o5 to ?1?, or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?.
a29l400 series preliminary (october, 2002, version 0. 2) 13 amic technology, inc. start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence. figure 3. program operation unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiate d by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two - cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles r equired in the standard program command sequence, resulting in faster total programming time. table 5 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid . to exit the unlock bypass mode, the system must issue the two - cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycle. the device returns to reading arr ay data. figure 3 illustrates the algorithm for the program operation. see the erase/program operations in ?ac characteristics? for parameters, and to program operation timings for timing diagrams. chip erase command sequence chip erase is a six - bus - cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set - up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the dev ice does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls o r timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the system can determine the st atus of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . see "write operation status" for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figur e 4 illustrates the algorithm for the erase operation. see the erase/program operations tables in "ac characteristics" for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a si x - bus - cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set - up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies t he sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time - out of 50 m s begins. during the time - out per iod, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less t han 50 m s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts
a29l400 series preliminary (october, 2002, version 0. 2) 14 amic technology, inc. start write erase command sequence data poll from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequences. 2. see "i/o 3 : sector erase timer" for more information. no figure 4. erase operation can be re - enabled after the last sec tor erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 m s, the system need not monitor i/o 3 . any command other than sector erase or erase suspend during the time - out period resets the device to r eading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor i/o 3 to determine if the sector erase timer has timed out. (see the " i/o 3 : sector erase timer" section.) the time - out begins from the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is comp lete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . refer to "write operation status" for information on these status bits. 4 illustra tes the algorithm for the erase operation. refer to the erase/program operations tables in the "ac characteristics" section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the er ase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 m s time - out period d uring the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time - out immediately terminates the time - out p eriod and suspends the erase operation. addresses are "don't cares" when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 m s to suspend the erase operation. ho wever, when the erase suspend command is written during the sector erase time - out, the device immediately terminates the time - out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device "erase suspends" all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase - suspended sectors produces status data on i/o 7 - i/o 0 . the system can use i/o 7 , or i/o 6 and i/o 2 together, to determine if a sector is actively erasing or is erase - suspended. see "write operation status" for information on these status bits. after an erase - suspended program operation is complet e, the system can once again read array data within non - suspended sectors. the system can determine the status of the program operation using the i/o 7 or i/o 6 status bits, just as in the standard program operation. see "write operation status" for more inf ormation. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see "autoselect command sequence" for more information. the system must write the erase resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing.
a29l400 series preliminary (october, 2002, version 0. 2) 15 amic technology, inc. tab le 5. a29l400 command definitions bus cycles (notes 2 - 5) first second third fourth fifth sixth command sequence (note 1) cycles addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 word 555 2aa 555 manufacturer id byte 4 aaa aa 555 55 aaa 90 x00 37 word 555 2aa 555 x01 b334 device id, top boot block byte 4 aaa aa 555 55 aaa 90 x02 34 word 555 2aa 555 x01 b3b5 device id, bottom boot block byte 4 aaa aa 555 55 aaa 90 x02 b5 word 555 2aa 555 x03 continuation id byte 4 aaa aa 555 55 aaa 90 x06 7f xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect (note 8) sector protect verify (note 9) byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30 legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory l ocation to be programmed. addresses latch on the falling edge of the we or ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we or ce pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a17 - a12 select a unique sector.
a29l400 series preliminary (october, 2002, version 0. 2) 16 amic technology, inc. note: 1. see table 1 for description of bus operations. 2. all values are in hexade cimal. 3. except when reading array or autoselect data, all bus cycles are write operation. 4. data bits i/o 15 ~i/o 8 are don?t care for unlock and command cycles. 5. address bits a17 - a11 are don't cares for unlock and command cycles, unless sa or pa required. 6. no u nlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if i/o 5 goes high (while the device is providing status data). 8. the fourth cycle of the autosel ect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 10. the unlock bypass command is required prior to the unlock bypass program command. 11. the un lock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. the system may read and program in non - erasing sectors, or enter the autoselect mode, when in the erase suspend mode. 13. the erase resume comma nd is valid only during the erase suspend mode.
a29l400 series preliminary (october, 2002, version 0.2) 17 amic technology, inc. write operation status several bits, i/o 2 , i/o 3 , i/o 5 , i/o 6 , i/o 7, ry/ by are provided in the a29l400 to determine the status of a write operation. table 6 and the following subsection s describe the functions of these status bits. i/o 7 , i/o 6 and ry/ by each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. i/o 7 : data polling the data polling bit, i/o 7 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on i/o 7 the complement of the datum programmed to i/o 7 . this i/o 7 status also applies to programming during erase s uspend. when the embedded program algorithm is complete, the device outputs the datum programmed to i/o 7 . the system must provide the program address to read valid status information on i/o 7 . if a program address falls within a protected sector, data polling on i/o 7 is active for approximately 2 m s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a "0" on i/o 7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on i/o 7 .this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to "1" ; prior to this, the device outputs the "complement," or "0." the system must provide an address within any of the sectors selected for erasure to read valid status information on i/o 7 . after an erase command sequence is written, if all sectors selected f or erasing are protected, data polling on i/o 7 is active for approximately 100 m s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects i/o 7 has changed from the complement to true data, it can read valid data at i/o 7 - i/o 0 on the following read cycles. this is because i/o 7 may change asynchronously with i/o 0 - i/o 6 while output enable ( oe ) is asserted low. the data polling timings (during embedded algorithms) in the "ac characteristics" section illustrates this. table 6 shows the outputs for data polling on i/o 7 . figure 5 shows the data polling algorithm. start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 5. data polling algorithm
a29l400 series preliminary (october, 2002, version 0.2) 18 amic technology, inc. ry/ by : read/ busy the ry/ by is a dedicated, open - drain output pin that indicates whether an embedded algorithm is in progre ss or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open - drain output, several ry/ by pins can b e tied together in parallel with a pull - up resistor to vcc. (the ry/ by pin is not available on the 44 - pin sop package) if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 6 shows the outputs for ry/ by . refer to ? reset timings?, ?timing waveforms for program operation? and ?timing waveforms for chip/sector erase operation? for more information. i/o 6 : toggle bit i toggle bit i on i/o 6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector e rase time - out. during an embedded program or erase algorithm operation, successive read cycles to any address cause i/o 6 to toggle. (the system may use either oe or ce to control the read cycles.) when the operati on is complete, i/o 6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, i/o 6 toggles for approximately 100 m s, then returns to reading array data. if not all selected sectors are protected, the em bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use i/o 6 and i/o 2 together to determine whether a sector is actively erasing or is erase - suspended. when the device is actively eras ing (that is, the embedded erase algorithm is in progress), i/o 6 toggles. when the device enters the erase suspend mode, i/o 6 stops toggling. however, the system must also use i/o 2 to determine which sectors are erasing or erase - suspended. alternatively, t he system can use i/o 7 (see the subsection on " i/o 7 : data polling"). if a program address falls within a protected sector, i/o 6 toggles for approximately 2 m s after the program command sequence is written, then returns to reading array data. i/o 6 also toggles during the erase - suspend - program mode, and stops toggling once the embedded program algorithm is complete. the write operation status table shows the outputs for toggle bit i on i/o 6 . refer to figure 6 for the toggle bit algorith m, and to the toggle bit timings figure in the "ac characteristics" section for the timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. see also the subsection on " i/o 2 : toggle bit ii". i/o 2 : toggle bit ii the "toggle bit ii" on i/o 2 , when used with i/o 6 , indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase - suspended. toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. i/o 2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but i/o 2 cannot distinguish whether the sector is actively erasing or is erase - suspended. i/o 6 , by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are sel ected for erasure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for i/o 2 and i/o 6 . figure 6 shows the toggle bit algorithm in flowchart form, and the section " i/o 2 : toggle bit ii" explains the al gorithm. see also the " i/o 6 : toggle bit i" subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. reading toggle bits i/o 6 , i/o 2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read i/o 7 - i/o 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on i/o 7 - i/o 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of i/o 5 is high (see the section on i/o 5 ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as i/o 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and i /o 5 has not gone high. the system may continue to monitor the toggle bit and i/o 5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the s ystem must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6).
a29l400 series preliminary (october, 2002, version 0. 2) 19 amic technology, inc. i/o 5 : exceeded timing limits i/o 5 indicates whether the program or erase time has exceeded a specified internal pulse count l imit. under these conditions i/o 5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully completed. the i/o 5 failure condition may appear if the system tries to program a "1 "to a location that is previou sly programmed to "0." only an erase operation can change a "0" back to a "1." under this condition, the device halts the operation, and when the operation has exceeded the timing limits, i/o 5 produces a "1." under both these conditions, the system must i ssue the reset command to return the device to reading array data. i/o 3 : sector erase timer after writing a sector erase command sequence, the system may read i/o 3 to determine whether or not an erase operation has begun. (the sector erase timer does no t apply to the chip erase command.) if additional sectors are selected for erasure, the entire time - out also applies after each additional sector erase command. when the time - out is complete, i/o 3 switches from "0" to "1." the system may ignore i/o 3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 m s. see also the "sector erase command sequence" section. after the sector erase command sequence is written, the system should read the status on i/o 7 ( data polling) or i/o 6 (toggle bit i) to ensure the device has accepted the command sequence, and then read i/o 3 . if i/o 3 is "1", the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignor ed until the erase operation is complete. if i/o 3 is "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of i/o 3 prior to and following each subsequent sector er ase command. if i/o 3 is high on the second status check, the last command might not have been accepted. table 6 shows the outputs for i/o 3 . start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes notes : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as i/o 5 changes to "1". see text. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation complete no no read i/o 7 -i/o 0 (notes 1,2) figure 6. toggle bit algorithm (note 1)
a29l400 series preliminary (october, 2002, version 0. 2) 20 amic technology, inc. table 6. write operation status i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 ry/ by operation (note 1) (note 2 ) (note 1) embedded program algorithm 7 i/o toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within n on - erase suspended sector data data data data data 1 erase suspend mode erase - suspend - program 7 i/o toggle 0 n/a n/a 0 notes: 1. i/o 7 and i/o 2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. i/o 5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?i/o5: exceeded timing limits? for more information. maximum negative input overshoot 20ns 20ns 20ns +0.8v -0.5v -2.0v maximum positive in put overshoot 20ns 20ns 20ns vcc +0.5v 2.0v vcc +2.0v
a29l400 series preliminary (october, 2002, version 0. 2) 21 amic technology, inc. dc characteristics cmos compatible (t a =0 c to 70 c or - 45 c to +85 c) parameter symbol parameter description test description min. typ. max. unit i li input load current v in = vss to vcc. vcc = vcc max 1.0 m a i lit a9 input load current vcc = vcc max, a9 =12.5v 35 m a i lo output leakage current v out = vss to vcc. vcc = vcc max 1.0 m a 5 mhz 4 10 ce = v il , oe = v ih byte mode 1 mhz 2 4 5 mhz 4 10 i cc1 vcc active read current (notes 1, 2) ce = v il , oe = v ih word mode 1 mhz 2 4 ma i cc2 vcc active write (program/erase) current (notes 2, 3, 4) ce = v il , oe =v ih 20 3 0 ma i cc3 vcc standby current (note 2) ce = v ih , reset = vcc 0.3v 0.2 5 m a i cc4 vcc standby current during reset (note 2) reset = vss 0.3v 0.2 5 m a i cc5 automatic sleep mode (note 2, 4, 5) v ih = vcc 0.3v ; v il = vss 0.3v 0.2 5 m a v il input low level - 0.5 0.8 v v ih input high level 0.7 x vcc vcc + 0.3 v v id voltage for autoselect and temporary unprotect sector vcc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0ma, vcc = vcc min 0.45 v v oh1 i oh = - 2.0 ma, vcc = vcc min 0.85 x vcc v v oh2 output high voltage i oh = - 100 m a, vcc = vcc min vcc - 0.4 v notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe at v ih . typica l vcc is 3.0v. 2. maximum i cc specifications are tested with vcc = vcc max. 3. i cc active while embedded algorithm (program or erase) is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30ns. typical sleep mod e current is 200na. 5. not 100% tested.
a29l400 series preliminary (october, 2002, version 0. 2) 22 amic technology, inc. dc characteristics (continued) zero power flash 0 500 1000 1500 2000 2500 3000 3500 4000 5 0 10 15 20 25 time in ns supply current in ma note: addresses are switching at 1mhz i cc1 current vs. time (showing active and automatic sleep currents) 1 2 3 4 5 0 2 4 6 8 10 frequency in mhz supply current in ma c 25 t : note = typical i cc1 vs. frequency 3.6v 2.7v
a29l400 series preliminary (october, 2002, version 0.2) 23 amic technology, inc. ac characteristics read only operations (t a =0 c to 70 c or - 45 c to +85 c) parameter symbols speed jedec std description test s etup - 70 - 90 unit t avav t rc read cycle time (note 1) min. 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max. 70 90 ns t elqv t ce chip enable to output delay oe = v il max. 70 90 ns t glqv t oe output enable to output delay max. 30 35 ns read min. 0 0 ns t oeh output enable hold time (note 1) toggle and data polling min. 10 10 ns t ehqz t df chip enable to output high z (notes 1) max. 25 30 ns t ghqz t df output enable to output high z (notes 1) 25 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first (note 1) min. 0 0 ns notes: 1. not 100% tested. 2. see test con ditions and test setup for test specifications. timing waveforms for read only operation addresses addresses stable ce oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v reset ry/by
a29l400 series preliminary (october, 2002, version 0. 2) 24 amic technology, inc. ac characteristics hardware reset ( reset ) (t a =0 c to 70 c or - 45 c to +85 c) parameter jedec std description test setup all speed options unit t ready reset pin low (during embedded algorithms) to read or write (see note) max 20 m s t ready reset pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset pu lse width min 500 ns t rh reset high time before read (see note) min 50 ns t rb ry/ by recovery time min 0 ns t rpd reset low to standby mode min 20 m s note: not 100% tested. reset timings ce, oe reset t rh t rp t ready reset timings not during embedded algorithms reset t rp ~ ~ reset timings during embedded algorithms ry/by ~ ~ t rb ~ ~ t ready ce, oe ry/by
a29l400 series preliminary (october, 2002, version 0. 2) 25 amic technology, inc. temporary sector unprotect (t a =0 c to 70 c or - 45 c to +85 c) parameter jedec std description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset setup time for temporary sect or unprotect min 4 m s note: not 100% tested. temporary sector unprotect timing diagram program or erase command sequence reset ~ ~ ~ ~ ~ ~ 12v 0 or 3v t vidr t vidr 0 or 3v t rsp ce we ry/by ~ ~
a29l400 series preliminary (october, 2002, version 0. 2) 26 amic technology, inc. ac characteristics word/byte configuration ( byte ) (t a =0 c to 70 c or - 45 c to +85 c) parameter all speed options jedec std description - 70 - 90 unit t elfl/ t elfh ce to byte switching low or high max 5 ns t flqz byte switching low to output high - z max 25 30 ns t hqv byte switching high to output active min 70 90 ns byte timings for read operations byte timings for write operations note: refer to the erase/program operations table for t as and t ah specifications. data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input t fhqv t flqz t elfh t elfl ce oe byte i/o 0 -i/o 14 i/o 15 (a-1) byte i/o 0 -i/o 14 i/o 15 (a-1) byte switching from word to byte mode byte switching from byte to word mode the falling edge of the last we signal t hold (t ah ) t set (t as ) ce byte we
a29l400 series preliminary (october, 2002, version 0. 2) 27 amic technology, inc. ac characteristics erase and program operations (t a =0 c to 70 c or - 45 c to +85 c) parameter speed jedec std description - 70 - 90 unit t avav t wc write cycle time (note 1) min. 70 90 ns t avwl t as address setup time min. 0 ns t wlax t ah address hold time min. 45 45 ns t dvwh t ds data setup time min. 35 45 ns t whd x t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghwl t ghwl read recover time before write ( oe high to we low) min. 0 ns t elwl t cs ce setup time min. 0 ns t wheh t ch ce hold time min. 0 ns t wlwh t wp write pulse width min. 35 35 ns t whwl t wph write pulse width high min. 30 ns byte typ. 5 t whwh1 t whwh1 byte programming operation (note 2) word typ. 7 m s t whwh2 t whwh2 sector erase operation (n ote 2) typ. 0.7 sec t vcs vcc set up time (note 1) min. 50 m s t rb recovery time from ry/ by min 0 ns t busy program/erase valid to ry/ by delay min 90 ns notes: 1. not 100% tested. 2. see the "erase and programming pe rformance" section for more information.
a29l400 series preliminary (october, 2002, version 0. 2) 28 amic technology, inc. timing waveforms for program operation addresses ce oe we data vcc a0h pd t wc pa program command sequence (last two cycles) pa d out ~ ~ ~ ~ pa ~ ~ status ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data (last two cycles) 555h t ah t whwh1 t ch t wp t wph t cs t ds t dh note : 1. pa = program addrss, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. ~ ~ t rb t busy ry/by
a29l400 series preliminary (october, 2002, version 0. 2) 29 amic technology, inc. addresses ce oe we data vcc 55h 30h t wc sa erase command sequence (last two cycles) va complete ~ ~ ~ ~ va ~ ~ in progress ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data 2aah t ah t whwh2 t ch t wp t wph t cs t ds t dh note : 1. sa = sector address (for sector erase), va = valid address for reading status data (see "write operaion ststus"). 2. illustratin shows device in word mode. 555h for chip erase 10h for chip erase ~ ~ t rb t busy ry/by timing waveforms for chip/sector erase operation
a29l400 series preliminary (october, 2002, version 0. 2) 30 amic technology, inc. timing waveforms for data polling (during embedded algorithms) addresses ce oe we i/o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ complement ~ ~ complement true valid data high-z status data ~ ~ status data true valid data high-z i/o 0 - i/o 6 t acc t ce t ch t oe t oeh t df t oh note : va = valid address. illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. ~ ~ t busy ry/by high-z
a29l400 series preliminary (october, 2002, version 0. 2) 31 amic technology, inc. timing waveforms for toggle bit (during embedded algorithms) note: va = valid address; not required for i/o 6 . illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. addresses ce oe we i/o 6 , i/o 2 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid status t acc t ce t ch t oe t oeh t df t oh va valid status valid status valid data ~ ~ (first read) (second read) (stop togging) ry/by ~ ~ t busy high-z
a29l400 series preliminary (october, 2002, version 0. 2) 32 amic technology, inc. timing waveforms for sector protect/unpr otect v id note : for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0 ~ ~ ~ ~ ~ ~ ~ ~ v ih reset sa, a6, a1, a0 data ce we oe valid* valid* valid* 60h 60h 40h status sector protect/unprotect verify 1us sector protect:150us sector unprotect:15ms
a29l400 series preliminary (october, 2002, version 0.2) 33 amic technology, inc. timing waveforms for i/o 2 vs. i/o 6 ac characteristics erase and program operations alternate ce controlled writes (t a =0 c to 70 c or - 45 c to +85 c) parameter speed jedec std description - 7 0 - 90 unit t avav t wc write cycle time (note 1) min. 70 90 ns t avel t as address setup time min. 0 ns t elax t ah address hold time min. 45 45 ns t dveh t ds data setup time min. 35 45 ns t ehdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghel t ghel read recover time before write ( oe high to we low) min. 0 ns t wlel t ws we setup time min. 0 ns t ehwh t wh we hold time min. 0 ns t eleh t cp ce pulse width min. 35 35 ns t ehel t cph ce pulse width high min. 30 ns byte typ. 5 t whwh1 t whwh1 programming operation (note 2) word typ. 7 m s t whwh2 t whwh2 sector erase operation (note 2) typ. 0.7 sec notes: 3. not 100% t ested. 4. see the "erase and programming performance" section for more information. enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce note : both i/o 6 and i/o 2 toggle with oe or ce. see the text on i/o 6 and i/o 2 in the section "write operation status" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
a29l400 series preliminary (october, 2002, version 0. 2) 34 amic technology, inc. timing waveforms for alternate ce controlled write operation addresses we oe ce data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling note : 1. pa = program address, pd = program data, sa = sector address, i/o 7 = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh ~ ~ ~ ~ reset ry/by erase and programming performance parameter typ. (note 1) max. (note 2) unit comments sector erase time 1.0 8 sec chip erase time 10 sec excludes 00h programming prior to erasure byte programming time 35 300 m s word programming time 12 500 m s byte mode 11 33 sec chip programming time (no te 3) word mode 7.2 21.6 sec excludes system - level overhead (note 5) notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc, 10,000 cycles. additionally, programming typically assumes checkerboard pattern. 2. under worst case condition s of 90 c, vcc = 2.7v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if the maximum byte program time give n is exceeded, only then does the device set i/o 5 = 1. see the section on i/o 5 for further information. 4. in the pre - programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system - level overhead is the time req uired to execute the four - bus - cycle command sequence for programming. see table 5 for further information on command definitions. 6. the device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
a29l400 series preliminary (october, 2002, version 0. 2) 35 amic technology, inc. latch - up characteristics descripti on min. max. input voltage with respect to vss on all i/o pins - 1.0v vcc+1.0v vcc current - 100 ma +100 ma input voltage with respect to vss on all pins except i/o pins (including a9, oe and reset ) - 1.0v 12.5v incl udes all pins except vcc. test conditions: vcc = 5.0v, one pin at time. tsop and sop pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 6 7.5 pf c out output capacitance v out =0 8.5 12 pf c in2 co ntrol pin capacitance v in =0 7.5 9 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0mhz data retention parameter test conditions min unit 150 c 10 years minimum pattern data retention time 125 c 20 years
a29l400 series preliminary (october, 2002, version 0. 2) 36 amic technology, inc. test conditions t est specifications test condition - 70 - 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 5 ns input pulse levels 0.0 - 3.0 0.0 - 3.0 v input timing measurement reference levels 1.5 1.5 v output timing measurement reference levels 1.5 1.5 v test setup 6.2 k w device under test c l diodes = in3064 or equivalent 2.7 k w 3.3 v
a29l400 series preliminary (october, 2002, version 0. 2) 37 amic technology, inc. ordering information top boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( m a ) package a29l400tm - 70 44pin sop a29l400tv - 70 48pin tsop a29l400tg - 70 70 4 20 0.2 48 - ball tfbga a29l400tm - 90 44pin sop a29l400tv - 90 48pin tsop a29l400tv - 90u 48pin tsop a29l400tg - 90 48 - ball tfbga a29l400tg - 90u 90 4 20 0.2 48 - ball tfbga bottom boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( m a ) package a29l400um - 70 44pin sop a29l400uv - 70 48pin tsop a29l400ug - 70 70 4 20 0.2 48 - ball tfbga a29l400um - 90 44pin sop a29l400uv - 90 48pin tsop a29l400uv - 90u 48pin tsop a29l400ug - 90 48 - ball tfbga a29l400ug - 90u 90 4 20 0.2 4 8 - ball tfbga
a29l400 series preliminary (october, 2002, version 0. 2) 38 amic technology, inc. package information sop 44l outline dimensions unit: inches/mm 1 l l 1 c 22 see detail f detail f 23 44 s d seating plane d y e h e a 1 a 2 a e b q 0.010" gauge plane dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.118 - - 3.00 a 1 0.004 - - 0.10 - - a 2 0.103 0.106 0.109 2.62 2.69 2.77 b 0.013 0.016 0.020 0.33 0.40 0.50 c 0.007 0.008 0.010 0.18 0.20 0.25 d - 1.122 1.130 - 28.50 28.70 e 0.490 0.496 0.500 12.45 12.60 12.70 e - 0.050 - - 1.27 - h e 0.620 0.631 0.643 15.75 16.03 16.33 l 0.024 0.032 0.040 0.61 0.80 1.02 l 1 - 0.0675 - - 1.71 - s - - 0.045 - - 1.14 y - - 0.004 - - 0.10 q 0 - 8 0 - 8 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
a29l400 series preliminary (october, 2002, version 0. 2) 39 amic technology, inc. package information tsop 48l (ty pe i) outline dimensions unit: inches/mm 1 e c d l q detail "a" 0.25 24 25 48 d 1 d y e s a 1 a 2 a detail "a" b dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.042 0.94 1.00 1.06 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20 d 0.779 0.787 0.795 19.80 20.00 20.20 d 1 0.720 0.724 0.728 18.30 18.40 18.50 e - 0.472 0.476 - 12.00 12.10 e 0.020 basic 0.50 basic l 0.016 0.020 0.024 0.40 0.50 0.60 s 0.011 typ. 0.28 typ. y - - 0.004 - - 0.10 q 0 - 8 0 - 8 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
a29l400 series preliminary (october, 2002, version 0. 2) 40 amic technology, inc. package information 48ld csp (6 x 8 mm) outline dimensions unit: mm (48tfbga ) a 1 h g f e d c b a top view side view c seating plane 1 2 3 4 5 6 bottom view ball*a1 corner h g f e d c b a e e 1 e e d 1 d b 0.10 c a dimensions in mm symbol min. nom. max. a - - 1.20 a 1 0.20 0.25 0.30 b 0.30 - 0.40 d 5.90 6.00 6.10 d 1 4.00 bsc e - 0.80 - e 7.90 8.00 8.10 e 1 5.60 bsc

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